1784 chessie lane, ottawa, il 61350 ? tel: 800/252-7074, 815/434-7800 ? fax: 815/434-8176
e-mail: sales@freqdev.com ? web address: http://www.freqdev.com -12 db to +60 db d83s series programmable amplifier features/benefits: ? full power bandwidth to 100 khz for wide dynamic range applications ? compact 1.8" x 0.8" x 0.3" (32 pin dip) size minimizes board space requirements ? serial interface and software protocol allowing operation on a simple three wire bus. ? data out line allows data verification and cascading of multiple amplifiers over the same serial interface. ? plug-in ready-to-use, reducing engineering design and manufacturing time. applications ? data acquisition ? test equipment ? remote instrumentation systems ? ground loop elimination in remote measurements ? improvements in system dynamic range and resolution ? telemetry ? process control ? digitally controlled auto ranging systems ? medical, scientific & engineering research description the d83s series programmable amplifiers are digitally controlled gain modules that were designed for condition- ing dc-coupled wide-band signals (ac coupled-optional). they are programmable from -12 db to +60 db in 6 db steps with an 8-bit serial data stream for gain selection using clock, data and strobe inputs. other standard performance features include differential input, single ended output, 5v interface logic, and low noise and distortion, making this plug-in ready-to-use amplifier ideal for many signal conditioning applications. available options include ac coupled input and/or differ- ential output. 5k 100 20 -20 +30 +40 +60 hz 50 1k 200 500 2k 10k 20k 50k 100k +70 +80 +50 d b g +20 +10 +0 -10 frequency response common mode rejection ratio 5k 100 20 -100 -50 -40 -20 hz 50 1k 200 500 2k 10k 20k 50k 100k -10 + 0 -30 d b g -60 -70 -80 -90 total harmonic distortion + noise 5k 100 20 -120 -70 -60 -40 hz 50 1k 200 500 2k 10k -30 -20 -50 d b g -80 -90 -100 -110 -10 +0
gain amplifier d83s series digital programming & control 1784 chessie lane, ottawa, il 61350 ? tel: 800/252-7074, 815/434-7800 ? fax: 815/434-8176
e-mail: sales@freqdev.com ? web address: http://www.freqdev.com the d83s programs via a three terminal serial data interface over a gain range from 0.25 (~-12db) to 1024 (~+60db) using c lock ( c ), s trobe ( s ) and d ata i nputs ( di ). a d ata o ut ( do ) connection is provided to permit cascading of multiple d83ss or looping of the input data to verify the programmed setting. two stages of programmable gain/attenuation are used to optimize the d-c offset and gain bandwidth performance. the gain programming equation is: g=[1+3xd0+12xd1+48xd2+64xd3]x[1/4+(1/4)xd4+(1/2)xd5+d6]x[1+3xd7] where d0 - d7 = 0 or 1 note: the use of the compliments of d0, d1, d2 and d3. c, s and di input specifications input data levels (cmos/ttl logic) input voltage (vd = 5vdc) low level in 0 vdc min., 1.5 vdc max. high level in 3.5 vdc min., 5.0 vdc max. input current low level in -10 -5 a typ., -1 a max. high level in +10 -5 a typ., +1 a max. input capacitance 5 pf typ., 7.5 pf max. recommended programming table all combinations of programming inputs produce valid gain settings as determined by the gain equation but can result in unusual values of gain. to minimize the multiplication of d-c offset and to maximize the bandwidth at high gains the following is the recommended programming format for binary weighted gains from 1/4 (~-12db) to 1024 (~60db). gain ( v/v ) gain (~db) d0 d1 d2 d3 d4 d5 d6 d7 1/4 -12.04 11110000 1/2 -6.02 11111000 10.00 11111100 2 +6.02 11111110 4 +12.04 01111100 8 +18.06 01111110 16 +24.08 00111100 32 +30.10 00111110 64 +36.12 00011100 128 +42.14 00001100 256 +48.16 00001110 512 +54.19 00001101 1024 +60.21 00001111 programming sequence the programming input circuit is a cd4094 series 8 bit shift register with latches. it requires an 8 bit input serial data stream, di (d0 to d7), a clock c to shift and a strobe s to latch the data (see note 1). a timing sequence must be observed to insure accurate shifting and latching of the input data. the input data bits, d0 through d7 are entered in reverse order, i.e. the msb, d7, is the first bit to be entered followed by d6 etc. and ending with the lsb, d0 (refer to timing diagram). 2
gain amplifier d83s series digital programming & control 1784 chessie lane, ottawa, il 61350 ? tel: 800/252-7074, 815/434-7800 ? fax: 815/434-8176
e-mail: sales@freqdev.com ? web address: http://www.freqdev.com the c lock shifts the input data di through the shift registers when it transitions from low to high. for the input data to be accurately received, it must have been present for at least ts at the time of the rising clock transition. the maximum clock pulse frequency is 1.25mhz. data from the shift registers propagates through the latches when the strobe is high. data is latched when the strobe transitions from high to low. to retain a programmed setting it is necessary to hold the strobe low (or to shut off the clock). keeping the strobe low will allow the clock to shift a new set of input data into the registers without changing the latched setting. to latch a new set of data the strobe must be set to its high state, after the last bit of the new input word (d0) has been shifted in (> tcs ), held high for a minimum time of tsw and then returned to its low state to latch and hold the setting. the return of s to its low state must occur before the rise of the clock that accepts the d7 of the next data word ( tsc >0). notes: 1.) data is shifted into register on positive edge of clock. 2.) data is latched on negative edge of strobe. 3.) ts is set up time (valid data before clock). 4.) tcs is time between d0 clock and start of strobe. 5.) tsw is strobe width. 6.) tsc is time between strobe end and d7 clock (next word). 7.) tcw is clock width. 8.) th is hold time (valid data after clock rising edge). minimum setup times ts >125ns time data must be present before rise of clock pulse. tcs >260ns time from rise of c lock for last data bit, d0, to rise of s trobe pulse. tsw >200ns s trobe w idth. tsc >0ns time from fall of s trobe to rise of next c lock pulse. tcw >200ns c lock pulse w idth. cf 1.25 mhz maximum c lock pulse f requency. th >5ns time data must be valid after rise of clock pulse. caution!! note 1: the c , p and di inputs are tri-state c-mos logic. they contain protection circuitry to guard against damage due to high static voltages or electric fields, however the application of any voltages higher than the +5v or lower than the 0v supply voltages can cause per manent damage. these inputs must always be connected to an appropriate logic voltage level. permanent damage can also result if c , p and di are allowed to float unconnected. if the d83s is used in a configuration where these inputs can become disconnected from their drive circuits, or i f their drive circuits are not powered by the same +5v source, it is recommended to use 10k ? pull up resistors to +5v on these inputs. =don't care strobe data d7 valid input d6 valid input d0 valid input d7 valid input ts tcw tcs tsc clock tsw th > 5ns timing diagram 3
specification (25c and vs 15 vdc) d83s series pin-out and package data ordering information 1784 chessie lane, ottawa, il 61350 ? tel: 800/252-7074, 815/434-7800 ? fax: 815/434-8176
e-mail: sales@freqdev.com ? web address: http://www.freqdev.com 4 ordering information analog input characteristics configuration dc coupled, differential input ac coupled (optional) fixed @ 10 hz impedance 1 m ? ?? 22pf bias current 20 pa max. offset current 10 pa max. voltage range 10 vpeak max. safe voltage vs common mode rejection ratio typ. 80 db @ 1 khz min. 60 db @ 1 khz noise voltage density, rti 20 nv/ hz @ 1 khz, g=1,024 analog output characteristics configuration single ended, dc coupled differential output (optional) impedance <1 ? typ., 10 ? max. current (linear operation) 5 ma max. offset voltage 2 mv rti, nte 40 mv max. offset temp. coeff. (5 + 100/g) v/?c general analog characteristics gain (programmable) 0.25x to 1,024x in factors of 2 gain tolerance 0.10 db distortion (0 db gain @ 3.5 vrms) -86 db @ 1 khz typ. full power bandwidth (0 db gain) 100 khz power supplies (vs), +vd rated voltage 15 vdc, +5 vdc operating range 5 to 18 vdc, 5 0.5 vdc maximum safe voltage 18 vdc, +5.5 vdc quiescent current 15 v 12 ma +5 v +0.2 ma temperature operating 0 to +70?c storage -25 to +85?c programmable instrumentation amplifier inverting amplifier +out -out do +in -in c di s programmable gain stage 4094 series 8 bit shift register ? ? 1.80 ? ? 0.30 ? 0.15 (min) side view ? ? 0.025 dia. s strobe all dimensions are in inches c clock all case dimensions 0.01" di data in grid dimensions do data out 0.10 x 0.10 note: nc pin is used as "-out" for differential output option +vs -in gnd bottom view -vs +5v s di c do +in +out nc/-out ? ? 0.80 (note) functional schematic d83s-d options a - ac coupled input d - differential output we hope the information given here will be helpful. the information is based on data and our best knowledge, and we consider t he information to be true and accurate. please read all statements, recommendations or suggestions herein in conjunction with our conditions of sale which apply to all goods supplied by us. we a ssume no responsibility for the use of these statements, recommendations or suggestions, nor do we intend them as a recommendation for any use which would infringe any patent or copyri ght. pr-00d83s-01
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